I. Field of the Invention
This invention relates generally to computer technology, and more particularly, to improving processor accuracy and reliability in a computer system.
II. Background Information
Early processors generally processed instructions one at a time. To improve efficiency, processor designers overlapped the operations of fetch, decode, and execute logic stages such that the processor operated on several instructions simultaneously. At each clock tick the results of each processing stage are passed to the following processing stage. Processors that use the technique of overlapping the fetch, decode, execute, and writeback stages are known as xe2x80x9cpipelinedxe2x80x9d processors.
In order for a pipelined processor to operate efficiently, an instruction fetch unit at the head of the pipeline must continually provide the pipeline with a stream of instructions. However, conditional branch instructions within an instruction stream prevent the instruction fetch unit from fetching subsequent instructions until the branch condition is resolved. In a pipelined processor, the branch condition will not be resolved until the branch instruction reaches an instruction execution stage further down the pipeline. The instruction fetch unit must stall since the branch condition is unresolved at the instruction fetch stage and therefore the instruction fetch unit does not know which instructions to fetch next.
To alleviate this problem, many pipelined processors use branch prediction mechanisms that predict the outcome of branch instructions within an instruction stream. The instruction fetch unit uses the branch predictions to fetch subsequent instructions.
When the branch prediction mechanism mispredicts a branch, an instruction execution unit further down the pipeline eventually detects the branch misprediction. After the instruction execution unit detects a branch misprediction, the instructions that should not have been fetched are flushed out (i.e., removed from the pipeline) of the processor pipeline and program execution resumes along the corrected instruction path. To properly resume execution along the correct path, the processor must obtain the address of the instruction that should have been executed after the branch instruction.
If a branch instruction is taken, the address of the next instruction to be executed after the branch instruction is the target address of the branch instruction. If this branch instruction is incorrectly predicted as not taken, after the correct target address of the branch target is evaluated by completing the execution of the branch instruction, the processor will flush the processor pipeline and resume execution along the correct instruction path by fetching the instruction at the branch instruction""s target address. This procedure is relatively simple since the target address is usually specified by the branch instruction and its associated operand.
On the other hand, if a branch instruction is not taken, the address of the next instruction to be executed after the branch instruction is the address of the instruction located sequentially after the branch instruction. By executing the branch instruction, this next sequential instruction address is evaluated. Again, if a misprediction is detected, the pipeline is flushed, and instruction fetch is resumed from this next sequential instruction address.
Between the different stages of the pipeline, latches may be used to store and transfer data between the different stages of the pipeline. As data is transferred from one stage to another, soft errors may occur in the latches. Soft errors in data storage elements, such as latches and memory cells occur when incident radiation charges or discharges the storage element thereby flipping its binary state. Soft errors are increasingly a concern with smaller scale fabrication processes as the size, and hence the capacitance of the storage elements get smaller and easier to disturb by incident radiation. While in the past soft errors were statistically significant only for large and dense storage structures like cache memories, with these smaller feature processes, soft errors are increasingly becoming a concern for pipeline latches as well, particularly wide (multi-bit) datapath latches, where probability of soft errors is most significant. When soft-errors silently corrupt data in a program, the program continues execution undetected other than producing the wrong results.
This Silent Data Corruption (xe2x80x9cSDCxe2x80x9d) is not desirable in mission critical applications such as commercial transaction server applications, where wrong results can have broad reaching implications. For this reason, at the very minimum, it is imperative that soft errors become detected when they occur, so at least the application can be terminated, and any data corruption detected and reported. A preferable option is on finding the error being able to correct it and seamlessly continue execution of the application. There is greater opportunity for correction by the processor hardware than by the system software due to the finer information granularity visible to the hardware.
Modern, high performance processors often have to make tradeoffs in terms of transistor count and die area on what features to add for improving performance and what to add for improving reliability. While both is desired, performance is usually given higher priority. Also, the processor should be optimized for the frequent case, i.e., when no soft errors occur. Therefore, the difficulty in processor design is to incorporate soft error checking and correcting mechanisms without decreasing the performance of the processor by adding more devices thus taking away the available area for performance features, adding more pipeline stages, or lowering its frequency.
For the foregoing reasons, there is a need to detect and correct soft errors such that the soft errors are detected and corrected without hindering processor performance and area.